1. Field of the Invention
Embodiments of the present invention generally relate to the processing of a metal layer on a substrate. More particularly, embodiments of the present invention relate to a method of annealing a copper layer on a substrate.
2. Background of the Related Art
Sub-quarter micron, multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
As circuit densities increase, the widths of vias, contacts, lines, plugs, and other features, generally decrease to less than a quarter of a micron. The thickness of the dielectric layers, however, generally remains substantially constant, with the result that the aspect ratios for the features, i.e., their height divided by width, increases. Due to copper's electrical performance at such small feature sizes, copper has become a preferred metal for filling sub-quarter micron, high aspect ratio interconnect features on substrates. However, many traditional deposition processes, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), have difficulty filling structures with copper material where the aspect ratio exceed 4:1, and particularly where the aspect ratio exceeds 10:1. As a result of these process limitations, electrochemical plating (ECP), which had previously been limited to the fabrication of lines on circuit boards, is now being used to fill vias and contacts on semiconductor devices.
A typical copper electroplating deposition method generally includes depositing a barrier layer via PVD or CVD over the surface of a substrate having various features formed thereon, depositing a metal (preferably copper) seed layer over the barrier layer, and then electroplating a metal layer (preferably copper) over the seed layer to fill the structure/feature. Finally, the deposited layers are planarized by a method such as chemical mechanical polishing (CMP), for example, to define a conductive interconnect feature.
ECP with copper presents some challenges in substrate manufacturing processes. For instance, ECP copper does not typically plate evenly across the substrate surface, leaving voids and discontinuities in the features. This unevenness is detrimental to circuit uniformity, conductivity, and reliability. Furthermore, ECP copper layers are susceptible to gradual oxidation from atmospheric conditions. This gradual oxidation results in increased electrical resistance of the copper layer. Additionally, since oxidation is typically a slow, gradual, and often variable process, copper layers from different sources plated at different times are likely to have undergone different levels of oxidation. This causes significant variability in subsequent processing of the copper layers.
To overcome problems associated with void formation as well as variation in copper oxidation, heat treatment of a film after deposition is generally performed. One effective technique for heat treating the film is annealing. Annealing is the process of subjecting a material to heat for a specific period of time, and then cooling the material. Annealing can be used to flow a plated metal layer to fill voids, purify layers, dope or encourage diffusion of layers, and manage crystal growth and orientation. More particularly, heat introduced during annealing allows the metal layer to flow and fill in voids in high aspect ratio features. Annealing also provides a thermodynamic driving force for the metal layers to form a predictable microstructure. A metal layer can, for example, be annealed in a particular atmosphere in order to provide a specific and predictable set of electrical properties (e.g. electrical resistivity).
Since copper has a relatively low melting temperature compared to other metals typically deposited in semiconductor manufacturing, copper is a promising candidate for annealing. New developments in semiconductor manufacturing that have focused on depositing copper, especially by ECP techniques, have sparked new interest in developing improved copper annealing processes. Additionally, copper deposited by ECP undergoes the physical phenomena of self-annealing. In self-annealing, copper undergoes microstructural changes after plating at room temperature. High temperature annealing can modify this self-annealing process that would otherwise take place in order to provide a consistent microstructure, as well as consistent electrical properties of the copper.
Current industry practice is to anneal copper layers while subjecting the layers to a high flow rate of nitrogen and hydrogen. Such high flow rates are typically necessary in order to prevent oxygen that is present in the chamber from oxidizing the copper during the anneal and thereby provide the low electrical resistivity required for semiconductor device applications. In a conventional annealing furnace, substrates are heated to about 250° C. to 400° C. for about 30 minutes, and then cooled to room temperature. Unfortunately, the high gas flow rates of conventional furnaces result in high degree of consumption of process gases per unit of copper layer that is processed. As a result, large quantities of process gas are required for processing, resulting in a high processing costs as well as wasted time associated with the continuous replacement of process gas storage containers. Therefore, there is a need to develop an annealing process that is effective at controlling the deleterious effects of atmospheric gases, yet consume reduced quantities of process gas during the annealing process.